Since early 2000’s, multicore processors have been 
identified as the most viable technology to continue our push
toward higher processor performance for a reasonable power 
and thermal budget, and are on the roadmap of almost every
major computer vendor today.  However, the idea of
multiprocessing has been with us for as long as electronic 
computers were first invented. Despite the impressive VLSI
technologies at our disposal today, the challenges we face
are as daunting as before. The main difference seems to be 
that we are really back to a corner this time with several 
very challenging “walls” around us: power “wall”, memory 
“wall”, ILP “wall”, frequency “wall” …, and multicore 
seems to be the only way out with very few other options in 
the near future.

For the users of these multicore systems, creating parallel 
programs are even more challenging than before because 
today’ systems are for a much wider spectrum of “general-
purpose” applications and no longer constrained to the 
specialized domains of supercomputing applications as in the 
past few decades. These challenges are further exacerbated by 
the power and thermal constraint in multicore processors. In 
addition, improving program performance is no longer our only 
goal as the increasing sophistication of software systems and 
their execution environment in multicore systems makes it 
possible to support better software programmability, 
testability and dynamic performance tuning.

In this talk, I first present our effort in optimizing 
“general-purpose” applications on multicore systems. Under 
the context of Thread-Level Speculation (TLS), we have 
implemented a compiler infrastructure to carry out code 
parallelization and optimizations. We also developed compiler 
and hardware supports to dynamically monitor performance, 
power and thermal behavior during program execution, and use 
the results to further optimize the code at runtime. I will 
then briefly discuss a monitoring framework that improves the 
programmability, testability and debuggability of software 
systems by facilitating the specification and creation of 
low-overhead program execution monitors. 


Short Bio:

Pen-Chung Yew is a professor in the Department of Computer 
Science and Engineering, University of Minnesota. He served 
as the Head of the department and the holder of the William-
Norris Land-Grant Chair Professor between 2000 and 2005. 
Before joining the University of Minnesota, he was an 
Associate Director of the Center for Supercomputing Research 
and Development (CSRD) at the University of Illinois at 
Urbana-Champaign. From 1991 to 1992, he served as the Program 
Director of the Microelectronic Systems Architecture Program 
in the Division of Microelectronic Information Processing 
Systems at the National Science Foundation, Washington, D.C.

Pen-Chung Yew is an IEEE Fellow. He served as the Editor-in-
Chief of the IEEE Transactions on Parallel and Distributed 
Systems between 2000 and 2005. He has also served on the 
program committee of many major conferences. He served as a 
co-chair of the 1990 International Conference on Parallel 
Processing (ICPP), a general co-chair of the 1994 
International Symposium on Computer Architecture (ISCA), the 
program chair of the 1996 International Conference on 
Supercomputing (ICS), a program co-chair of the 2002 
International Conference on High Performance Computer 
Architecture (HPCA), a program co-chair of 2004 Asian-Pacific 
Computer Systems Architecture Conference (ACSAC), and the 
general chair of 2006 International Conference on Parallel 
and Distributed Systems (ICPADS).