This paper describes a design of adjustable convolutional hardware in image processing. As performing an n×n convolution traditionally needs n² processing elements (PEs), therefore, the larger the mask size is, the more the number of PEs and the cost are. In order to achieve a reasonable performance/cost ratio, we design a new architecture using n or less PEs to perform an n×n convolution. This hardware architecture together with a few delay-line buffers is designed in pipeline-and-paralle1 fashion. Presently, a 3×3 convolutional prototype consisting of only two PEs has been constructed on a single board and can approximately operate in real-time.

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3. A Computing Architecture of Adjustable Convolution System for Image Processing
   
4. Fast Progressive Image Transmission without Table Look-Up, Computation and Error Propagation
   
5. A New 2D Quadrature Mirror FIR Filters for Image Sub-Band Coding
   
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