July 31, 1998 Updated by Ms. Jade Y.S. Hsu
Vol.3 No.1, pp.63-79 (January 1987)

A Computing Architecture of Adjustable Convolution
System for Image Processing

Po-Ning Chen*, Yung-Sheng Chen* and Wen-Hsing Hsu*,**
*Institute of Electrical Engineering,
National Tsing Hua University,
**Institute of Information Science,
Academia Sinica

        This paper describes a design of adjustable convolutional hardware in image processing. As performing an nn convolution traditionally needs n2 processing elements (PEs), therefore, the larger the mask size is, the more the number of PEs and the cost are. In order to achieve a reasonable performance/cost ratio, we design a new architecture using n or less PEs to perform an nn convolution. This hardware architecture together with a few delay-line buffers is designed in pipeline-and-paralle1 fashion. Presently, a 33 convolutional prototype consisting of only two PEs has been constructed on a single board and can approximately operate in real-time.

JISE

  1. Machine Vision for Industry Prospects and Future Trends
  2. A Model-Constrained Rule-Based Pattern Matching System for Object Recognition
  3. A Computing Architecture of Adjustable Convolution System for Image Processing
  4. Fast Progressive Image Transmission without Table Look-Up, Computation and Error Propagation
  5. A New 2D Quadrature Mirror FIR Filters for Image Sub-Band Coding
  6. Image Restoration Using a Nonstationary Image Model
  7. Texture Synthesis in Image Processing and Computer Graphics