CRISC is a 32-bit single-chip VLSI processor architecture that achieves high performance by means of RISC and multiple functional unit approaches. Dual ALUs are used to execute instructions concurrently for fine-grained parallelism.

        As semiconductor technologies advance, more devices and, thus, multiple functional units, can be accommodated in a single VLSI chip. However, the multifunctional unit approach complicates software design. Detailed and careful analyses of hardware-software design trade-offs thus become very important.

        In this paper, the concepts of RISC and overlapped execution are presented. CRISC architecture design considerations and on-chip instruction cache scheme are investigated. The final microarchitecture and its incorporated software technique to produce object code for fine-grained parallel execution is described, and its performance upper bound is estimated by an architectural model. Moreover, a preliminary evaluation of CRISC is conducted, which shows very satisfying results.

Keywords: code compaction, concurrent execution, RISC, VLSI processor, on-chip cache

Received March 10, 1989; revised September 1, 1989.
Communicated by Wen-Tsuen Chen.