Kai Hwang and Dhabaleswar K. Panda
Laboratory for Parallel Computing
University of Southern California
Los Angeles, CA 90089-0781, USA
In this paper, we report the design experience and some new research results of a multiprocessor architecture to support image processing and matrix computations. We identify the architectural requirements for an integrated image understanding system. The hardware architectural features of a 16-processor orthogonal multiprocessor prototype system are presented. Designs of architectural supporting blocks are emphasized to support high-performance matrix structured computation, image processing, vision, and neural computing applications. This system is targeted to achieve a peak performance of 400 RISC integer MIPS or a maximum of 640 Mflops. We report simulated performance results of this prototype and emphasize on the scalability issues of this architecture to higher dimensions for solving problems requiring multi-dimensional matrix data structures.
Keywords: multiprocessor, parallel processing, matrix algarithms, image understanding, neural simulation
Received May 13, 1991; revised November 1, 1991.
Communicated by Wen-Tsuen Chen.
*This research was supported by USA/NSF Grant No. 89-04172.
The results have been presneted in the 1990 ACM International Conference on Supercomputing, Amsterdam, Jaune 11-15, 1990.