Yen-Jen Oyang, Chun-Hung Wen, Ching0Chuan Chiang,
Ching-Te Lin, Yu-Fen Chen, Shu-May Lin,
Chao-Yi Fang, Fu-Li Chen and Chou-Yu Ku
Department of Computer Science and Information Engineering
National Taiwan University
Taipei, Taiwan, R.O.C.
This paper elaborates the major architectural features of the Spectra-I superscalar microprocessor. The design of Spectra-I is aimed at exploiting multi-way branch operations to boost superscalar processor performance. This objective is achieved with the development of a compiler technique called the SV transformation and a new hardware multi-way branching mechanism. Preliminary performance analysis shows that Spectra-I, with two parallel execution units, achieves a speedup of 1.62 over a typical RISC processor.
Keywords: superscalar microprocessor, multi-way branch, instruction-level parallelism, static instruction scheduling, RISC
Received June 1, 1991; revised November 1, 1991.
Communicated by Ferng-Ching Lin.
*This research was supported by National Science Council of R.O.C. under the contract NSC 80-0408-E-002-15.