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Journal of Inforamtion Science and Engineering, Vol.14 No.3, pp.633-644 (September 1998)
Entity Overloading for Mixed-Signal Abstraction
in VHDL*

C.-J. Richard Shi
Department of Electrical and Engineering
University of Washington
Seattle, WA 98195-2500, U.S.A.

In this paper we propose to extend VHDL with entity overloading. With minimal change in the existing VHDL, entity overloading provides strong support for mixed-signal, mixed-level, and mixed-domain abstractions. It is particularly promising for resolving some issues related to analog extension of VHDL. Furthermore, we show that entity overloading can be combined with certain modeling rules to obtain a polymorphic netlist.

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Received October 31, 1997; revised March 18, 1998.
Communicated by Jin-Yang Jou.
* An early version of this paper was presented at the European Design Automation Conference (EuroDAC'96), Geneva, Switzerland, September, 1996, and received a Best Paper Award Nomination from the Conference Technical Program Committee. This work was sponsored by the U.S. Defense Advanced Research Projects Agency (DARPA) under grant number F33615-96-1-5601 from the United States Air Force, Wright Laboratory, Manufacturing Technology Directorate. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the author and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied of the U.S. Government.