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Journal of Inforamtion Science and Engineering, Vol.14 No.3, pp.669-686 (September 1998)
A Two-Phase Fault Simulation Scheme
for Sequential Circuits

Wen Ching Wu, Chung Len Lee and Jwu E Chen*
Department of Electronic Engineering
National Chiao Tung University
Hsinchu, Taiwan 300, R.O.C.
*Department of Electrical Engineering
Chung-Hua University
Hsinchu, Taiwan 300, R.O.C.

A two-phase fault simulation scheme for sequential circuits is proposed. In this fault simulation, the input sequence is divided into two parts. In the first phase, fault free simulation is performed with the first sequence of patterns. In the second phase, fault simulation is performed with the rest of the patterns. Five cases of faults which result from two-phase fault simulation are discussed in detail. Significant speedup in simulation time can be obtained because this fault simulation approach can quickly drop Case 1 faults, which are time-consuming faults and would be considered undetectable in the traditional three-value fault simulation but are actually detected in exact fault simulation. Almost "exact" results can be obtained for detected faults except for a small percentage of over-detected-faults (ODFs) and under-detected-faults (UDFs).

Keywords: computer-aided-design, digital testing, sequential circuits, fault simulation, untestable faults

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Received June 1, 1996; revised May 23, 1997.
Communicated by Youn-Long Lin.