Chao-Chin Wu and Cheng Chen
Department of Computer Science and Information Engineering
National Chiao Tung University
Hsinchu, Taiwan 300, R. O. C.
The release consistency model is the generally accepted hardware-centric relaxed memory consistency model because of its performance and implementation complexity. By extending the release consistency model, in this paper, we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessor systems with parallel-multithreaded processing elements. The new model uses a new categorization for memory references and utilizes the feature of parallel multithreaded processors (PMPs). We further partition acquire and release references into three sub-categories: one for lock-unlock pairs, one for barrier synchronization, and the last for others. According to the semantic of each synchronization primitive, each sub-category has its own relaxed restrictions. On the other hand, the feature of a PMP is that it is capable of executing more than one thread at the same time, where all parallel threads share only one cache hierarchy. Under the new model, we can use dual write-caches to reduce write traffic and synchronization time.
We have used five benchmarks in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, the new model is superior to the release consistency model at best by about 11%.
Keywords: memory consistency model, multihread, multiprocessor, write cache, synthronization, PSC model, barrier, performance evaluation
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Received May 24, 1997; accepted February 24, 1998.
Communicated by Youn-Long Lin.