Ing-Jer Huang and Li-Rong Wang
Institute of Computer and Information Engineering
National Sun Yat-Sen University
Kaohsiung, Taiwan 804, R.O.C.
This paper presents a methodology for automatic simulation and verification of pipelined microcontrollers. Using this methodology, we can generate the simulation for the instruction set architecture (ISA), abstract finite state machine (FSM) and pipelined register transfer level design and compare the simulation results across different levels quickly. We have implemented our method in the simulation and verification of a synthesized microcontroller HT_4 using our behavioral synthesis tool.
Keywords: functional verification, simulation, high level synthesis, microcontrollers, microprocessors
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Received October 31, 1997; accepted March 18, 1998.
Communicated by Youn-Long Lin.