Vol. 16 No. 5 (September 2000)

SPECIAL ISSUE ON VLSI TESTING

1. Testable Path Delay Fault Cover for Sequential Circuits
   Angela Krstic, Srimat T. Chakradhar and Kwang-Ting Cheng......pp. 673-686
   
   

2. Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits
   Hsing-Chung Liang and Chung Len Lee......pp. 687-702
   
   
3. Compact Test Generation Using a Frozen Clock Testing Strategy
   Elizabeth M. Rudnick and Miron Abramovici.......pp. 703-717
   
   
4. Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches
   Sying-Jyan Wang and Chia-Chun Lien.....pp. 719-731
   
   
5. Testing Configurable LUT-Based FPGAs
   Shyue-Kung Lu and Jen-Sheng Shih.......pp. 733-750
   
   

6. A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier
   Yeong-Jar Chang, Chung Len Lee, Jwu E Chen and Chauchin Su......pp. 751-766
   
   

7. Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis
   Chauchin Su, Yue-Tsang Chen and Shen-Shung Chiang......pp. 767-781
   
   

8. A Probabilistic Model for Path Delay Fault Testing
   Chih-Yuang Su and Cheng-Wen Wu......pp. 783-794