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Journal of Inforamtion Science and Engineering, Vol. 16 No. 5, pp. 673-686 (September 2000)

Testable Path Delay Fault Cover for Sequential Circuits*

Angela Krstic, Srimat T. Chakradhar+
and Kwang-Ting (Tim) Cheng Department of ECE
University of California
Santa Barbara, CA 93106, U.S.A.
+C & C Research Laboratories
NEC USA
Princeton, NJ 08540, U.S.A.

We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit, or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is a smaller fault set and possibly a smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or do not have to be examined for delay defects.

Keywords: delay testing, path delay faults, timing defects, sequential circuits, untestable path delay faults

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Received July 21, 1999; revised December 23, 1999; accepted March 15, 2000.
Communicated by Cheng-Wen Wu.
*This work was supported by NEC USA, Inc., by MICRO and by the National Science Foundation under Grant MIP-9409174.