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Journal of Inforamtion Science and Engineering, Vol. 16, No. 5, pp. 687-702 (September 2000)

Flip-Flop Selection for Mixed Scan and Reset Design Based
on Test Generation and Struture of
Sequential Circuits*

Hsing-Chung Liang and Chung Len Lee
Department of Electronic Engineering
Chang Gung University
Taoyuan, Taiwan 333, R.O.C.
E-mail: hcliang@mail.cgu.edu.tw
+Department of Electronics Engineering
National Chiao Tung Unviersity
Hsinchu, Taiwan 300, R.O.C.
E-mail: cllee@cc.nctu.edu.tw

In this paper, a novel mixed selection methodology using flip-flops for scan and reset design is proposed. The method runs test generation for a sequential circuit to obtain reachable states of flip-flops and required states for hard-to-detect faults. The circuit is also explored so as to acquire the structural connection relationship among the flip-flops. By analyzing these three sets of information, the flip-flops can be arranged in an appropriate order for mixed partial scan and reset selection. Instead of selecting the best flip-flop to revise the circuit for the next test generation, we give first priority to independent flip-flops each time in order to reduce the number of iterations. Experimental results show that this method can achieve higher testability with fewer scan/reset flip-flops than can either the scan only or the previous mixed scan/reset methods.

Keywords: partial scan, partial reset, reachable states, test generation, design for testability

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Received June 30, 1999; revised December 23, 1999; accepted March 7, 2000.
Communicated by Kuen-Jong Lee.
*This work was supported in part by the National Science Council, Taiwan, R.O.C. under Grant NSC-88-2215-E238-002.