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Journal of Inforamtion Science and Engineering, Vol. 16 No. 5, pp. 703-717 (September 2000)

Compact Test Generation Using a Frozen Clock Testing Strategy*

Elizabeth M. Rudnick and Miron Abramovici+
Center for Reliable and High-Performance Computing
University of Illinois
Urbana, IL, U.S.A.
Lucent Echnologies
Murray Hill, NJ, U.S.A.

Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.

Keywords: automatic test generation, compact test sets, frozen clock testing strategy, sequential circuit testing, test vector compaction

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Received June 29, 1999; revised September 14, 1999; accepted March 7, 2000.
Communicated by Cheng-Wen Wu.
*This research was supported in part by DARPA under Contract DABT63-95-C-0069 and in part by Hewlett-Packard under an equipment grant.