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Journal of Inforamtion Science and Engineering, Vol.17 No.2, pp.229-243 (March 2001)

Design and Analysis of an ATM Switch
With Priority Discarding Scheme*

Kuochen Wang and Hsin-Jung Wang+
Department of Computer and Information Science
National Chiao Tung University
Hsinchu, Taiwan 300, R.O.C.
+Second Operation and Maintenance
Pacific Cellular Corporation
Chungli, Taiwan 320, R.O.C.

In this paper, we propose an N ? N high speed and non-blocking asynchronous transfer mode (ATM) switch with input and output buffers. In this switch, each buffer adopts a priority discarding scheme, which discards incoming cells of low-priority traffic when its queue length is greater than a predefined threshold value. Our switch also supports broadcast/multicast functions without increasing the cost and imposing a significant performance penalty. We use the discrete-time Markov chain model to analyze cell delay and cell loss probability for each traffic class. An example 4 ? 4 ATM switch has been described with VHDL. We have verified the functionality of the switch via VHDL simulation, and have synthesized the switch to evaluate its area and timing. Experimental results and synthesis results show that our proposed ATM switch can meet a requirement for high speed and support QOS.

Keywords: ATM switch, multiple-bus, VHDL, QOS, high speed, priority discarding scheme

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Received August 29, 1998; revised September 30 & December 2, 1999; accepted January 18, 2000.
Communicated by Nen-Fu Huang.
* This research was supported in part by the National Science Council, R.O.C., under Grant NSC85-2213- E-009-120.