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Journal of Inforamtion Science and Engineering, Vol.17 No.5, pp.787-803 (September 2001)

Aggressive Scheduling for Memory Accesses of
CISC Superscalar Microprocessors

R-Ming shiu, Hui-Yue Hwang and Jean Jyh-Jiun Shann
Department of Computer Science and Information Engineering
National Chiao Tung University
Hsinchu, 300 Taiwan

For CISC microprocessors, the proportion of memory access instructions is relatively high, and a specific address is likely to be accessed repeatedly in a short period of time because of register-to-memory or memory-to-memory instruction set architectures and limited register sets. As superscalar architectures advance, an aggressive scheduling policy for memory access becomes crucial. In this paper, we examine the scheduling policies of loads/stores on CISC superscalar processors and develop an aggressive scheduling policy called preload. The preload scheduling policy allows loads to precede the earlier unsolved pending stores, and delays the checking of conflict and forwarding of data until the data is loaded, thereby allowing greater tolerance of the latency for address generation. Because of its popularity, we focus our attention on the x86 instruction set. Simulation results show that the preload achieves a higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the preload can achieve even higher performance.

Keywords: CISC, superscalar, memory access ordering, x86 microprocessor, load bypassing, load forwarding

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Received January 6, 2000; revised May 25, 2000; accepted September 26, 2000.
Communicated by Youn-Long Lin.
* This paper presents partial result of a long-term research project financed by both the NSC of R.O.C. under contract no. NSC 86-2622-E-009-009 and the industry.