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VLSI Design of RSA Cryptosystem Based on

the Chinese Remainder Theorem

**Chung-Hsien Wu, Jin-Hua Horng ^{*} and Cheng-Wen Wu**

Department of Electrical Engineering

National Tsing Hua University

Hsinchu, 300 Taiwan

Da-Yeh University

Changhua, 515 Taiwan

This paper presents the design and implementation of a systolic RSA cryptosystem based on a modified Montgomery¡¦s algorithm and the Chinese Remainder Theorem (CRT) technique. The CRT technique improves the throughput rate up to 4 times in the best case. The processing unit of the systolic array has 100% utilization because of the proposed block interleaving technique for multiplication and square operations in the modular exponentiation algorithm. For 512-bit inputs, the number of clock cycles needed for a modular exponentiation is about 0.13 to 0.24 million. The critical path delay is 6.13ns using a 0.6£gm CMOS technology. With a 150 MHz clock, we can achieve an encryption/decryption rate of about 328 to 578 Kb/s.

Keywords: cellular array, Montgomery algorithm, modular multiplication, Chinese remainder theorem (CRT), RSA, public-key cryptography

Retrieve PDF document (**200111_07.pdf**)

Received January 31, 2001; accepted July 10, 2001.

Communicated by Chi Sung Laih