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Journal of Information Science and Engineering, Vol. 20 No. 6, pp. 1231-1238 (November 2004)

Logic Rewiring for Dealy and Power Minimization*

Andreas Veneris
Department of Electrical and Computer Engineering
and Department of Computer Science
University of Toronto
Toronto, Ontario M5S 3G4, Canada
E-mail: veneris@eecg.tononto.edu

An application of the ATPG-based method by Veneris et al. [11] to multi-level combinational logic circuit delay and power optimization is presented. A number of theoretical results and various heuristics are described to allow for an efficient implementation of the algorithm. Experiments confirm the robustness of the approach.

Keywords: VLSI, logic optimization, low power, design performance, diagnosis

Full Text () Retrieve PDF document (200411_12.pdf)

Received November 1, 2002; revised September 16, 2003; accepted November 10, 2003.
Communicated by Liang-Gee Chen.
*Parts of this work are also presented in: A. Veneris, M. Amiri, and I. Ting, "Design Rewiring for Power Minimization," in IEEE Internatinal Symposium on Circuits and Systems, 2002.