¡@

Fuzzy logic has been successfully applied in various fields, but these applications have usually suffered from the problem of low speed. Typically, calculation of the matching degree requires very high latency, which limits the overall inference speed. In this paper, we prove that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set. Based on this analysis, we present an effective hardware unit that can be used to obtain the matching degree very quickly. Moreover, a pipelined parallel VLSI fuzzy inference processor is proposed to take advantage of our basic idea. The proposed hardware architecture has been implemented using 0.35?m process technology. To the best of our knowledge, our fuzzy inference processor is the only existing architecture that can tackle 64 rules with fuzzified inputs at a speed of 7 MFLIPS.

Keywords: digital design, hardware design, high performance, fuzzy logic, fuzzy inference

Retrieve PDF document (200505_07.pdf)

Received December 16, 2003; revised July 19, 2004; accepted November 15, 2004.
Communicated by Liang-Gee Chen.
^* A preliminary version, entitled "A High-Speed VLSI Fuzzy Logic Controller with Pipeline Architecture," has appeared in the Proceedings of IEEE International Conference on Fuzzy Systems (FUZZ-IEEE), 2001.