Previous [ 1] [ 2] [ 3] [ 4] [ 5] [ 6] [ 7] [ 8] [ 9] [ 10] [ 11] [ 12] [ 13]

@

Journal of Information Science and Engineering, Vol. 22 No. 1, pp. 215-227 (January 2006)

Advanced High-Level Cache Management by Processor Access Information

Jong Wook Kwak, Cheol Hong Kim, Sunghoon Shim and Chu Shik Jhon
Department of Electrical Engineering and Computer Science
Seoul National University
Seoul, 151-742 Korea
E-mail: leoniss@panda.snu.ac.kr

In this paper, we propose an advanced high-level cache management policy based on the processor access information, named as L1VPAI (L1 plus Victim cache with Processor Access Information). The L1VPAI is a cache replacement policy that uses the frequency of the specific cache line. In this policy, conflicted lines in the L1 cache are placed selectively in the victim cache or the level 2 (L2) cache based on previous memory access patterns. In this manner, the L1VPAI policy can make the frequently used address of cache locations reside longer in the high-level caches. We simulate our policy with RSIM, the event-driven simulator, and analyze the simulation results. The simulation results show that the average execution time of the L1VPAI outperforms the simple victim cache (L1V) by up to 6.44%. Moreover, performance gain is expected to increase, in the case of multiprocessor systems.

Keywords: hierarchical memory system, L1 cache, victim cache, cache replacement policy, processor access information

Full Text () Retrieve PDF document (200601_13.pdf)

Received February 19, 2004; revised June 11 & November 18, 2004; accepted December 22, 2004.
Communicated by Chu-Sing Yang.