Previous [ 1] [ 2] [ 3] [ 4] [ 5] [ 6] [ 7] [ 8] [ 9] [ 10] [ 11] [ 12] [ 13] [ 14] [ 15] [ 16]


Journal of Information Science and Engineering, Vol. 22 No. 4, pp. 975-989 (July 2006)

Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications

Kuo-Hsing Cheng and Shun-Wen Cheng+
Department of Electrical Engineering
National Central University
Taoyuan 32001, Taiwan
+Department of Electronic Engineering
Far East College
Tainan 74448, Taiwan

This paper presents an improved 32-bit conditional sum adder. Due to architectural modification, the improved adder only selects and transmits carry signals; it therefore is named conditional carry adder (CCA). This 32-bit adder focuses on reducing the num-bers of internal nodes and logical gates, while maintaining high speed. The 32-bit condi-tional sum adder uses 186 multiplexers, and the proposed 32-bit CCA only uses 129 multiplexers. Consequently, the proposed adder is attractive for use in low-power arith-metic systems. Conventional single-end static CMOS and differential-end CPL circuits were used to implement and compare the proposed 32-bit CCA. Experimental and con-trol chips were designed and fabricated using 0.5gm CMOS technology. Simulations and measurements under various supply voltages showed that the 32-bit CCA achieved high performance in low-voltage high-speed applications.

Keywords: 32-bit, differential-end logic, pass-transistor logic, conditional sum adder, carry select adder, low-voltage, high-speed, CMOS design

Full Text () Retrieve PDF document (200607_16.pdf)

Received June 8, 2004; revised October 5 & December 20, 2004; accepted January 5, 2005.
Communicated by Chung-Yu Wu.