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Journal of Information Science and Engineering, Vol. 22 No. 5, pp. 1229-1247 (September 2006)

Bounding DMA Interference on Hard-Real-Time Embedded Systems*

Tai-Yi Huang, Chih-Chieh Chou and Po-Yuan Chen
 Department of Computer Science
National Tsing Hua University
Hsinchu, 300 Taiwan
E-mail: {tyhuang; ccchou; pychen}@cs.nthu.edu.tw

A DMA controller that operates in the cycle-stealing mode transfers data by stealing bus cycles from the CPU. The concurrent contention for the I/O bus by a CPU task and a cycle-stealing DMA I/O task retards their progress and extends their execution times. In this paper we first describe a method for bounding the worst-case execution time (WCET) of a CPU task when cycle-stealing DMA I/O is present. We next use the dynamic- programming technique to develop a method for bounding the WCET of a cyclestealing DMA I/O task executing concurrently with a set of CPU tasks. We conducted exhaustive simulations on a widely-used embedded processor. The experimental results demonstrate that our methods tightly bound the WCETs of CPU tasks and of cycle- stealing DMA I/O tasks.

Keywords: hard-real-time systems, worst-case execution time, cycle-stealing DMA I/O, concurrent execution, embedded systems

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Received June 21, 2004; accepted November 1, 2004.
Communicated by David H. C. Du.
*This work was supported in part by the Ministry of Economic Affairs of Taiwan, under grant No. MOEA 95-EC-17-A-01-S1-038 and 94-EC-17-A-04-S1-044.