JISE Vol.22 No.6 #18

Journal of Information Science and Engineering, Vol. 22 No. 6, pp. 1585-1599 (November 2006)

Using Stack Reconstruction on RTL Orthogonal Scan Chain Design^*

Chia-Chun Tsai⁺, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee and Jan-Ou Wu
⁺Department of Computer Science and Information Engieering
Nanhua University
Chiayi, 622 Taiwan
E-mail: chun@mail.nhu.edu.tw
Graduate Institute of Computer and Communication Engineering
National Taipei University of Technology
Taipei, 106 Taiwan

In this paper, we propose an orthogonal scan chain embedded into the RTL design described by Verilog. We first construct the data path graph from the embedded scan chains and then find all the orthogonal scan paths with the minimum weighted cost. These paths share with original data paths as possible. Finally, we create a stack form to reconstruct all the orthogonal scan paths to manage the I/Os and reduce the length and width of stack form as well as decrease the overheads of area and timing. Experimental results show our RTL orthogonal scan chain approach can save up to 13.8% and 5.1% in area overhead than that of the gate-level scan and functional order RTL scan, respectively.

Keywords: RTL scan, orthogonal scan chain, area overhead, timing overhead, fault coverage

Retrieve PDF document (200611_18.pdf)

Received September 20, 2004; revised December 3, 2004 & March 11, 2005; accepted April 7, 2005.
Communicated by Liang-Gee Chen.
^* The work was supported in part by the National Science Council of Taiwan, R.O.C., under grant No. NSC 92-2220-E-027-001.