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Chichyang Chen and Rui-Lin Chen
Department of Information Engineering and Computer Science
Feng Chia University
Taichung, 407 Taiwan
Pipelined computation of very large word-length logarithmic number system (LNS)
addition/subtraction requires a lot of hardware and long pipeline latency. This paper
proposes a base-e exponential algorithm to simplify the exponential computation and to
replace half of the pipeline stages by multiplication-and-accumulate operations. By using
this approach, the circuit area and the pipeline latency of the previously proposed 64-bit
basic LNS addition/subtraction unit can be reduced by 42.4% and 39.22%, respectively.
Based on the base-e exponential algorithm approach, we also develop signed- digit (SD)
exponential, SD discretization, and SD on-line logarithmic algorithms to further increase
the throughput and to reduce the pipeline latency of the LNS computation. From our
synthesis results, the throughput of the 64-bit LNS unit can be increased by 61.9% and
the pipeline latency can be reduced by 55.0%, without increasing the hardware cost of
the basic LNS unit. The circuit area of the 64-bit hardware-reduced LNS unit is estimated
to be only 6.89 times the circuit area of a comparable 64-bit floating-point unit.
We conclude that the proposed approaches have significantly improved the performance
of the previously proposed LNS unit and have made a significant progress towards the
implementation of very large word-length LNS arithmetic.
Received June 17, 2005; revised September 16 & October 18, 2005 & March 3, 2006; accepted April 25, 2006.
Communicated by Liang-Gee Chen.
*This work was supported by the National Science Council of Taiwan, R.O.C. under contract No. NSC 91-
2213-E-035-017.