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¡@
Chao-Hung Lu, Hung-Ming Chen** and Chien-Nan Jimmy Liu
Department of Electrical Engineering
National Central University
Taoyuan, 320 Taiwan
E-mail: {chlu; jimmy}@ee.ncu.edu.tw
**Department of Electronics Engineering and SoC Research Center
National Chiao Tung University
Hsinchu, 300 Taiwan
E-mail: hmchen@mail.nctu.edu.tw
As VLSI technology enters the nanometer era, the supply voltage is continually
dropped. This condition helps to reduce the power dissipation, but make the power integrity
problem become worse. Employing decoupling capacitances (decap) at floorplan
stage has been a common approach to alleviate the supply noise problem. However, the
decap budget is often overly estimated in previous researches. Besides the decap budget
computation, the available floorplan space does not fully used in previous works. In one
floorplan, it usually has many available spaces except the empty space that could be used
to insert the decap without increasing the floorplan area. Therefore, our goal in this work
is to develop a better model to calculate the required decap to solve the power supply
noise problem of area-array based designs and to increase he usage of the available space
in the floorplan to reduce the area overhead caused by decap insertion. The experimental
results are encouraging. Compared with other approaches, our algorithm can reduce
52.6% decap budget on the MCNC benchmarks but still keep the power supply noise in
the given constraint. The final floorplan areas with decap are also less than the numbers
reported in previous papers.
Received February 2, 2007; accepted July 13, 2007.
Communicated by K. Robert Lai, Yu-Chee Tseng and Shu-Yuan Chen.
*This work was supported in part by the National Science Council of Taiwan, R.O.C. under contract NSC
96-2220-E-009-016 and NSC 96-2221-E-008-120.