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Arthur M. D. Shr1,2, Alan Liu1 and Peter P. Chen2
1Department of Electrical Engineering and Center for Telecommunication Research
National Chung Cheng University
Chiayi, 621 Taiwan
E-mail: arthurshr@gmail.com; aliu@ee.ccu.edu.tw
2Department of Computer Science
Louisiana State University
Baton Rouge, LA 70803, U.S.A.
E-mail: {mshr1; pchen}@lsu.edu
We propose a Load Balancing (LB) scheduling approach to tackle the load balancing
issue in the semiconductor manufacturing system. This issue is derived from the
dedicated photolithography machine constraint. The constraint of having a dedicated
machine for the photolithography process in semiconductor manufacturing is one of the
new challenges introduced in photolithography machinery due to natural bias. To prevent
the impact of natural bias, the wafer lots passing through each photolithography
process have to be processed on the same machine. However, the previous research for
the semiconductor manufacturing production has not addressed the load balancing issue
and dedicated photolithography machine constraint. In this paper, along with providing
the LB approach to the issue, we also present a novel model, Resource Schedule and
Execution Matrix (RSEM) ¡V the representation and manipulation methods for the task
process patterns. The advantage of the proposed approach is to easily schedule the wafer
lots by using a simple two-dimensional matrix. We also present the simulation results to
validate our approach.
Received January 9, 2006; revised September 21, 2006; accepted January 23, 2007.
Communicated by Suh-Yin Lee.
*This research was partially supported by the U.S. National Science Foundation grant No. IIS-0326387 and
U.S. AFOSR grant No. FA9550-05-1-0454. This research was also supported in part by the Ministry of
Economic Affairs under the grant No. 96-EC-17-A-02-S1-029 and the National Science Council under the
grants No. 96-2752-E-008-002-PAE and 95-2221-E-194-009.