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A two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that the test data and test time are reduced by 64% and 35%, respectively. This technique requires no change of cores and hence provides a feasible SOC test compaction solution for the SOC integrators.

Keywords: test compression, SOC testing, test time reduction, design for testability, computer-aided design, IEEE 1500

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Received June 27, 2006; revised October 2, 2006 & February 7 & May 21, 2007; accepted June 26, 2007.
Communicated by Liang-Gee Chen.
^*This research was partly supported by the National Science Council of Taiwan, R.O.C. under contract No. NSC 92-2220-E-002-006 and by the Ministry of Economy under the contract No. MOE 94-EC-17-A-01-S1- 031.