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Due to the fast development of multimedia and communication applications, reconfigurable computing which has the great potential to accelerate a wide variety of applications is getting more and more important in computer architecture and software system. By mapping the computationally intense portions of an application into hardware, the application could be greatly accelerated. Reconfigurable computing incorporates the benefits of implementations of software and hardware. In this paper, we propose a novel reconfigurable processing unit, FMRPU, which is a fine-grain with multi-context reconfigurable processing unit targeting at high-throughput and data-parallel applications. It contains 64 reconfigurable logic arrays, 16 switch boxes, and connects with each other via three hierarchical-level connectivities. According to the simulation results, the longest routing path of FMRPU only takes 6.5 ns at 0.35 processes, which is able to construct the required logic circuit efficiently. To compare with same kind devices in dealing with Motion Estimation operations, the performance is raise to 17% and has excellent performance in executing DSP algorithms.

Keywords: fine-grain reconfigurable architecture, multi-context, reconfigurable processing unit, FPGA, reconfigurable computing

Retrieve PDF document (200805_19.pdf)

Received June 6, 2006; revised October 11, 2006 & January 17 & May 24, 2007; accepted June 27, 2007.
Communicated by Liang-Gee Chen.