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Journal of Information Science and Engineering, Vol. 24 No. 3, pp. 981-991 (May 2008)

A Register Array Based Low Power FFT Processor for Speech Recognition*

Gin-Der Wu and Ying Lei
Department of Electrical Engineering
National Chi Nan University
Puli, 545 Taiwan

Fast Fourier Transform (FFT) plays an important role in the field of digital signal processing. High performance FFT processors are widely used in different application, such as speech processing, image processing, and communication system. In this paper, we proposed a novel register array based low power FFT processor for Mel Frequency Cepstral Coefficient (MFCC). Compared with [9-12], this novel architecture can reduce more power consumption. This approach is very attractive for the speech feature extraction of MFCC.

Keywords: digital signal processing, FFT processor, register array, low power, Mel Frequency Cepstral Coefficient (MFCC)

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Received January 5, 2007; revised April 4 & May 24, 2007; accepted June 22, 2007.
Communicated by Liang-Gee Chen.
*This work was supported by the National Science Council of Taiwan, R.O.C. under grant NSC 94-2213-E- 260-010. The preliminary version of this paper has been presented in 2006 IEEE Conference on Systems of Systems Engineering, Los Angeles, CA, U.S.A.