Keywords: asynchronous circuit, microcontroller, micropipeline, dual-rail, Muller pipeline, quasi-delay-insensitive
Received May 10, 2007; revised November 6, 2007 & March 17, 2008; accepted July 17, 2008.
Communicated by Yao-Wen Chang.
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Chang-Jiu Chen, Wei-Min Cheng, Hung-Yue Tsai and Jen-Chieh Wu
Department of Computer Science
National Chiao Tung University
Hsinchu, 300 Taiwan
Microcontrollers are widely used on simple systems; thus, how to keep them operating
with high robustness and low power consumption are the two most important issues.
It is widely known that asynchronous circuit is the best solution to address these
two issues at the same time. However, it¡¦s not very easy to realize asynchronous circuit
and certainly very hard to model processors with asynchronous pipeline. That¡¦s why
most processors are implemented with synchronous circuit. There are several ways to
model asynchronous pipeline. The most famous of all is the micropipeline; in addition,
most micropipeline based asynchronous systems are implemented with single-rail bundled-
delay model. However, we implemented our 8-bit microprocessor core for asynchronous
microcontrollers with an alternative ¡V the Muller pipeline. We implemented
our microprocessor core with dual-rail quasi-delay-insensitive model with Verilog
gate-level design. The instruction set for the target microprocessor core is compatible
with PIC18. The correctness was verified with ModelSim software, and the gate-level
design was synthesized into Altera Cyclone FPGA. In fact, the model we used in this
paper can be applied to implement other simple microprocessor core without much difficulty.
Received May 10, 2007; revised November 6, 2007 & March 17, 2008; accepted July 17, 2008.
Communicated by Yao-Wen Chang.