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Journal of Information Science and Engineering, Vol. 25 No. 2, pp. 575-589 (March 2009)

FPGA Implementation of a Recurrent Neural Fuzzy Network with On-Chip Learning for Prediction and Identification Applications*

Cheng-Jian Lin and Chi-Yung Lee+
 Department of Computer Science and Information Engineering
National Chin-Yi University of Technology
Taichung County, 411 Taiwan
+Department of Computer Science and Information Engineering
Nankai University of Technology
Nantou County, 542 Taiwan

In this paper, a hardware implementation of a recurrent neural fuzzy network (RNFN) used for identification and prediction is proposed. A recurrent network is embedded in the RNFN by adding feedback connections in the second layer, where the feedback units act as memory elements. Although the back propagation (BP) learning algorithm is widely used in the RNFN, BP is too complicated to be implemented using hardware. However, we use the simultaneous perturbation method as a learning scheme for hardware implementation to overcome the above-mentioned problems. The hardware implementation of the RNFN uses random access memory (RAM), which stores all the parameters of a network. This design method reduces the number of logic gates used. The major findings of the experiment show that field programmable gate arrays (FPGA) implementation of the RNFN retains good performance in identification and prediction problems.

Keywords: recurrent neural fuzzy network (RNFN), field programmable gate array (FPGA), simultaneous perturbation learning, random access memory (RAM), prediction, identification

Full Text (¥þ¤åÀÉ) Retrieve PDF document (200903_15.pdf)

Received May 8, 2007; revised November 6, 2007, May 21 & July 15, 2008; accepted August 22, 2008.
Communicated by Yao-Wen Chang.
* This work was supported by National Science Council, R.O.C., under grant NSC 97-2221-E-167-022.