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SHIH-HSU HUANG, CHUN-HUA CHENG AND DA-CHEN TZENG
Department of Electronic Engineering
Chung Yuan Christian University
Chungli, 320 Taiwan
E-mail: {shhuang; g9402601; g9476017}@cycu.edu.tw
Leakage current minimization is an important topic for event driven applications
that spend most of their times in standby mode. Power gating technique is one of the most
effective ways to reduce the standby leakage current. However, when power gating technique
is applied to a functional unit, there exists a delay-power tradeoff, which can be
characterized with the widths of sleep transistors. In this paper, we point out that: under
the same target clock period, there are many feasible clock skew schedules; since different
clock skew schedules impose different timing constraints to functional units, different
clock skew schedules may lead to different standby leakage currents. Based on that observation,
we present an MILP (mixed integer linear programming) approach to formally
formulate the problem of simultaneous application of optimal clock skew scheduling and
power-gated module selection (i.e., sleep transistor width selection) in high-level synthesis
stage. Experimental data show that: compared with the existing design flow, our
standby leakage current reduction achieves 29.3%.
Received March 7, 2008; revised July 15 & December 3, 2008; accepted December 11, 2008.
Communicated by Yao-Wen Chang.
* This work was supported in part by the National Science Council of Taiwan, R.O.C., under contract No. NSC
96-2628-E-033-004-MY3.