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Journal of Information Science and Engineering, Vol. 25 No. 6, pp. 1839-1853 (November 2009)

Efficient Header Classification Architecture for Network Intrusion Detection

WEN-JYI HWANG AND CHIEN-MIN OU*
Department of Computer Science and Information Engineering
National Taiwan Normal University
Taipei, 117 Taiwan
*Department of Electronics Engineering
Ching Yun University
Chungli, 320 Taiwan

In this paper, an efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

Keywords: network intrusion detection system, FPGA implementation, pattern matching, header classification architecture, shift-or algorithm

Full Text () Retrieve PDF document (200911_11.pdf)

Received December 12, 2007; revised June 10 & September 22, 2008; accepted October 16, 2008.
Communicated by Tzong-Chen Wu.