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Journal of Information Science and Engineering, Vol. 26 No. 2, pp. 585-595 (March 2010)

Low Parasitic Capacitance and Low-Power CMOS Capacitive Fingerprint Sensor*

MENG-LIEH SHEU, WEI-HUNG HSU AND YUAN-CHANG HUANG
Department of Electrical Engineering
National Chi Nan University
Puli, Nantou, 545 Taiwan

In this paper, a low parasitic capacitance and low-power CMOS capacitive fingerprint sensor readout circuit is presented. The side effect of parasitic capacitance has been under control with novel layout structure in sensor cell, and minimal size switch is used to reduce non-ideal effects of MOS switch and achieve good linearity. Power dissipation is also reduced with quiescent current control in buffer amplifier of sensor cell. A prototype chip with 32 32 array size has been fabricated using TSMC 0.35gm CMOS process. The chip works at 3.3V power supply and operates at 4MHz clock rate. Capacitance value from 0fF to 60fF can be sensed, corresponding analog output voltage is from 3.02V to 1.57V and the digital output is 6 bits. The overall power consumption is less than 5.5mW.

Keywords: biometric technology, fingerprint sensor, low-power, capacitive sensing, SAR ADC

Full Text () Retrieve PDF document (201003_15.pdf)

Received March 18, 2008; revised July 14, 2008; accepted August 28, 2008.
Communicated by Liang-Gee Chen.
* This work has been partially supported by the National Science Council of Taiwan, R.O.C., under grant No. NSC 96-2221-E-260-027. The authors would like to thank Chip Implementation Center (CIC) for the help on chip fabrication.