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Journal of Information Science and Engineering, Vol. 26 No. 2, pp. 631-648 (March 2010)

An Efficient Architecture of Extended Linear Interpolation for Image Processing

CHUNG-CHI LIN1, MING-HWA SHEU2, HUANN-KENG CHIANG2, CHISHYAN LIAW1, ZENG-CHUAN WU3 AND WEN-KAI TSAI2
1Department of Computer Science
Tung Hai University
Taichung, 407 Taiwan
2Graduate School of Engineering Science and Technology
3Department of Electronic Engineering
National Yunlin University of Science and Technology
Yunlin, 640 Taiwan

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost and high-speed architecture with interpolation quality compatible to that of bi-cubic convolution interpolation. The method of reducing computational complexity of generating weighting coefficients is proposed. Based on the approach, the efficient hardware architecture is designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The architecture is implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13gm standard cell library. The simulation results demonstrate that the efficient VLSI of extended linear interpolation at 267MHz with 25980 gates in a 450 450gm2 chip is able to process digital image scaling for HDTV in real-time.

Keywords: interpolation, scaling, image reconstruction, bi-cubic convolution, VLSI

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Received March 17, 2008; revised August 20, 2008 & February 5, 2009; accepted April 9, 2009.
Communicated by Tong-Yee Lee.