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Journal of Information Science and Engineering, Vol. 26 No. 4, pp. 1273-1288 (July 2010)

The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA

JIH-CHING CHIU, YU-LIANG CHOU AND TSENG-KUEI LIN
Department of Electrical Engineering
National Sun Yat-sen University
Kaohsiung, 804 Taiwan

The potential performance of superscalar processors can be exploited only when processor is fed with sufficient instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs could not support instruction streaming beyond a basic block. In x86 processors, the split-line instruction problem worsens this situation. In this paper, we proposed a basic blocks reassembling ISB. By cooperating with the proposed Line- Weighted Branch Target Buffer (LWBTB), the proposed ISB can predict upcoming branch information and reassemble current cache line together with the other cache line containing instructions for the next basic block. Therefore, the fetcher could fetch more instructions in a cycle with the assistance of the proposed ISB. Simulation results show that the cache line size over 64 bytes has a good chance to let two basic blocks present in a reassembled cache line and the fetch efficiency is about 90% as the fetch capacity is under 6.

Keywords: trace cache, instruction stream buffer, ILP, superscalar processor, x86 architecture, multiple instruction fetch

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Received June 4, 2008 revised May 27 & August 17, 2009; accepted October 1, 2009.
Communicated by Chung-Ping Chung.