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CHE-HUA SHIH+, YA-CHING YANG, CHIA-CHIH YEN, JUINN-DAR HUANG AND JING-YANG JOU
Department of Electronics Engineering
National Chiao Tung University
Hsinchu, 300 Taiwan
+E-mail: matar@eda.ee.nctu.edu.tw
Verifying whether a building block conforms to a specific interface protocol is one
of the important steps in a platform-based system-on-a-chip design methodology. There
are limitations for most of the existing methods for interface protocol compliance verification.
Simulation-based methods have the false positive problem while formal property
checking methods may suffer from memory explosion and excessive runtime. In this paper,
we propose a novel approach for interface protocol compliance verification. The
properties of the interface protocol are first specified as a specification FSM. Then the
compliance of interface logic is formally verified at the higher FSM level so that the required
memory and runtime can be greatly reduced. Finally, it is shown theoretically and
experimentally that the proposed algorithm possesses acceptably low time complexity for
practical applications.
Received October 17, 2008; revised March 9 & June 22, 2009; accepted July 17, 2009.
Communicated by Yao-Wen Chang.
* The previous version of this paper has been presented in the IEEE International Symposium on VLSI Design,
Automation, and Test, April 2005, pp. 12-15.