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JER-MIN JOU AND YUN-LUNG LEE
Department of Electrical Engineering
National Cheng Kung University
Tainan, 701 Taiwan
A new optimal arbiter is designed. We proposed a set of optimal Boolean functions
and the corresponding circuit for it, and showed that the arbitration Boolean functions
derived are optimal (simplest). This new arbiter is fair for any input combinations and
faster than all previous arbiters we knew. Using Synopsys design tools with TSMC
0.18£gm technology, the design results have shown that our arbiter has 22.8% improvement
of execution time and 39.1% of cost (area) reduction compared with the existing
fastest arbiter, SA [7]. Because of this small arbiter¡¦s the high-performance, it is extremely
useful for the realizations of NoC routers, MPSoC arbitration, and ultra-high- speed
switches. This new arbiter is being applied for a patent of the R.O.C. (application No.:
0972020612-0).
Received February 11, 2009; revised August 3 & November 6, 2009; accepted January 5, 2010.
Communicated by Tei-Wei Kuo.
* This work has been presented in part by International Computer Symposium, 2008, pp. 288-293.