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The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits its smallest standby leakage current its power gating can achieve. In this paper, we point out that, in the high-level synthesis of a nonzero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work formulating the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage- current resource binding solution. Benchmark data show that, compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.

Keywords: high-level synthesis, integer linear programming, power gating, clock skew optimization, resource binding

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Received November 16, 2009; revised March 24 & July 27, 2010; accepted August 16, 2010.
Communicated by Chung-Ping Chung.
^* This work was supported in part by the National Science Council of Taiwan, R.O.C., under Grant No. NSC 96- 2628-E-033-004-MY3. A preliminary version of this paper, entitled ¡§Timing Driven Power Gating in High- Level Synthesis¡¨ [25], has been presented in the 14th Asia and South Pacific Design Automation Conference (ASPDAC), 2009.