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Journal of Information Science and Engineering, Vol. 27 No. 1, pp. 287-302 (January 2011)

Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits

CHAO-HUNG LU, HUNG-MING CHEN* AND CHIEN-NAN JIMMY LIU
Department of Electrical Engineering
National Central University
Taoyuan, 320 Taiwan
E-mail: {chlu; jimmy}@ee.ncu.edu.tw
*Department of Electronics Engineering
National Chiao Tung University
Hsinchu, 300 Taiwan
E-mail: hmchen@mail.nctu.edu.tw

Billions of transistors are placed in one single chip (SoC) with advanced manufacturing technology. Further development is obstructed by the ability to the manufacture of SoC and the signal integrity. Stacking IC is an alternative choice when we design a highperformance high-density chip. Design flow (especially physical design) is facing different issues when compared with 2D IC design. The location of the I/Os seriously affect the number of 3D-Vias and their total area in the stacking IC. This paper proposes a Stacking IC architecture and the corresponding design flow to solve the I/O and 3D-Via problems. In this flow, we have developed a system partition approach to minimize the number of 3D-Vias and balance the I/O number of each tier, and modified one traditional floorplan method to optimize the I/O and module locations. The experimental results are encouraging in the GSRC benchmarks. Compared with greedy and intuitive methods, our framework reduces the number of 3D-Vias by 30.02% on the average and can balance the I/O count of each tier. The dead space of the final floorplan is reduced by 14.13%.

Keywords: stacking IC, partition, floorplanning, TSV, 3D-via

Full Text () Retrieve PDF document (201101_18.pdf)

Received January 5, 2009; revised June 17, 2009; accepted August 20, 2009.
Communicated by Yao-Wen Chang.