| Previous | [ 1] | [ 2] | [ 3] | [ 4] | [ 5] | [ 6] | [ 7] | [ 8] | [ 9] | [ 10] | [ 11] | [ 12] | [ 13] | [ 14] | [ 15] | [ 16] | [ 17] | [ 18] | [ 19] | [ 20] | [ 21] | [ 22] | [ 23] | [ 24] | [ 25] |
¡@
HANKOOK JANG1, SANG-HWA CHUNG1,+, DONG KYUE KIM2 AND YUN-SUNG LEE1
1Department of Computer Engineering
Pusan National University
Busan, 609-735 Korea
2Division of Electronics and Computer Engineering
Hanyang University
Seoul, 133-791 Korea
To achieve both the flexibility of software and the performance of hardware, we design
a hybrid architecture for a TCP offload engine that is based on hardware/software
co-design. In this architecture, the transmission and reception paths of TCP/IP are completely
separated with the aid of two general embedded processors to process data transmission
and reception simultaneously. We implement this architecture based on an FPGA
that has two general embedded processor cores. In the experiments based on the gigabit
Ethernet, the hybrid TOE has a minimum latency of 13.5 £gs. The CPU utilization is less
than 3%, which is at least eighteen times lower than that of the general gigabit Ethernet
adapters. The maximum unidirectional bandwidth of the hybrid TOE is 110 MB/s -
comparable to that of the general gigabit Ethernet adapters - although the embedded
processors operate with a clock speed that is seven times lower than that of the host CPU.
By using two embedded processors, the bidirectional bandwidth of the hybrid TOE improves
to about 201 MB/s, comparable to that of the general gigabit Ethernet adapters,
and a 34% improvement over an experimental TOE implementation in which only one
embedded processor is used.
Received May 27, 2009; revised September 9 & December 11, 2009; accepted February 9, 2010.
Communicated by Ren-Hung Hwang.
* This work was supported by the Grant of the Korean Ministry of Education, Science and Technology (The
Regional Core Research Program/Institute of Logistics Information Technology).
+ Corresponding author.