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Journal of Information Science and Engineering, Vol. 27 No. 2, pp. 643-656 (March 2011)

SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories*

TSU-WEI TSENG AND JIN-FU LI
Department of Electrical Engineering
National Central University
Chungli, 320 Taiwan

Variability in transistor performance will continue to increase with the scaling of technology. Transistors are more and more unreliable. Also, the noise-tolerant capability of circuits is less and less robust. To avoid the loss of yield and fault coverage, the design- for-testability circuit must be designed to be noise-tolerant. This paper presents a soft-error tolerant built-in self-test (SETBIST) design for random access memories (RAMs). Some soft-error-mitigation (SEM) techniques are proposed to enhance the softerror immunity of the instruction register, March operation generator, address generator, and data background generator. Experimental results show that the area overhead of the SETBIST is only about 1.1% for an 8K 64-bit SRAM. Analysis results show that the SETBIST can effectively tolerate soft errors. We also use FPGA demonstration board to verify the SETBIST scheme.

Keywords: fault-tolerance, built-in self-test, memory test, random access memories, reliability

Full Text () Retrieve PDF document (201103_15.pdf)

Received April 1, 2009; revised June 17, 2009; accepted August 20, 2009.
Communicated by Yao-Wen Chang.
* This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contract No. NSC 97-2215-E-008-095-MY3 and MOEA, Taiwan, under Contract No. 96-EC-17-A-01-S1-002.