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Journal of Information Science and Engineering, Vol. 27 No. 5, pp. 1513-1526 (September 2011)

Minimum Inserted Buffers for Clock Period Minimization*

SHIH-HSU HUANG+, GUAN-YU JHUO AND WEI-LUN HUANG
Department of Electronic Engineering
Chung Yuan Christian University
Chungli, 320 Taiwan
+E-mail: shhuang@cycu.edu.tw

It is well known that the combination of clock skew scheduling and delay insertion can achieve the lower bound of sequential timing optimization. Previous works focus on the minimization of required inserted delay. However, from the viewpoint of design closure, minimizing the number of inserted buffers is also very important. In this paper, we propose an MILP (mixed integer linear programming) approach to minimize the number of inserted buffers under the constraints on the lower bound of sequential timing optimization and the lower bound of required inserted delay. Note that our MILP approach guarantees obtaining the optimal solution. Experimental results consistently show that our MILP approach can greatly reduce the number of inserted buffers.

Keywords: high performance, sequential circuits, timing optimization, clock period, buffer insertion

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Received May 21, 2010; revised August 9 & November 1, 2010; accepted November 28, 2010.
Communicated by Yao-Wen Chang.
* A preliminary version, entitled ¡§Minimum Buffer Insertions for Clock Period Minimization¡¨ [15], has appeared in the Proceedings of IEEE International Symposium on Computer, Communication, Control and Automation (3CA), 2010. This work was supported in part by the National Science Council of Taiwan, R.O.C., under grant No. NSC 99-2221-E-033-061-MY3.