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Recent progress in process technology makes it possible to vertically stack multiple integrated chips. In three dimensional integration circuits (3D ICs), through silicon vias (TSVs) are used to communicate signals between layers. However, TSVs act as obstacles during placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic in 3D IC design. However, previous high-level synthesis approach only tries to maximize the number of same-layer operation-level datatransfers. In fact, a TSV should correspond to a cross-layer resource-level data-transfer. Therefore, in this paper, we propose an integer linear programming (ILP) approach to perform TSV number minimization by minimizing the number of cross-layer resource-level data-transfers. Experimental results consistently show that our approach is more effective than the previous approach in TSV number minimization.

Keywords: electronic design automation, high-level synthesis, three dimensional integration circuits, layer assignment, through silicon via

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Received February 12, 2010; revised July 21, 2010; accepted November 3, 2010.
Communicated by Yao-Wen Chang.
^* This work was supported in part by the National Science Council of Taiwan, R.O.C., under grant No. NSC 97- 2221-E-033-053-MY3.
¹ Although TSVs result in many negative impacts, they are helpful to the reduction of heat dissipation. Therefore, some physical design researches [15, 16] studied the addition of dummy TSVs for the reduction of heat dissipation. However, in the high-level synthesis stage, the design of 3D IC still focuses on the minimization of TSV number.
² In this paper, the term "dependency relation" and the term "data-transfer" are used interchangeably.