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I-WEI WU, CHUNG-PING CHUNG AND JEAN JYH-JIUN SHANN
Department of Computer Science
National Chiao Tung University
Hsinchu, 300 Taiwan
Instruction set extension (ISE) is an effective approach to improve the processor
performance without tremendous modification in its core architecture. To execute ISE(s),
a processor core must be augmented with a new functional unit, called application specific
functional unit (ASFU), which consists of multiple hardware implementation options
of ISEs (ISE_HW). Obviously, since ISE_HW increases the production cost of a
processor core, minimizing the area size of ISE_HW becomes important for ISE exploration.
On the other hand, because of different requirements in space and speed, ISE_HW
usually has multiple hardware implementation options. Under pipeline-stage timing constraint,
some of these options may have the same performance improvement but entail
different hardware costs. According to this phenomenon, the area size of ISE_HW can be
reduced by performing hardware design space exploration of ISE_HW. Therefore, in this
paper, we propose an ISE exploration algorithm that explores not only ISE but also the
hardware design space of ISE_HW. Compared with the previous research, our approach
resulted in significant improvement in area efficiency and the execution performance.
Received December 14, 2009; revised April 6, 2010; accepted June 14, 2010.
Communicated by Pen-Chung Yew.
* This paper was partially supported by the National Science Council of R.O.C. under contract No. NSC 98-
2221-E-009-158-MY3.