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Journal of Information Science and Engineering, Vol. 27 No.
5, pp. 1712-1727 (September 2011)
A Low-Memory Address Translation Mechanism
for Flash-Memory Storage Systems*
CHIN-HSIEN WU, CHEN-KAI JAN+ AND TEI-WEI KUO++
Department of Electronic Engineering
National Taiwan University of Science and Technology
Taipei, 106 Taiwan
+Department of Electrical Engineering
Chang Gung University
Taoyuan, 333 Taiwan
++Department of Computer Science and Information Engineering
National Taiwan University
Taipei, 106 Taiwan
While flash-memory has been widely adopted for various embedded systems, the
performance of address translation has become a critical issue for the design of flash translation
layers. The aim of this paper is to improve the performance of existing designs by
proposing a caching mechanism for efficient address translation. A replacement strategy
with low-time complexity and low-memory requirements is proposed to cache the most
recently used logical addresses. According to the experiments, the proposed method has
shown its efficiency in the reducing of the address translation time.
Keywords:
rflash memory, caching mechanism, embedded systems, storage systems, low
memory
Retrieve PDF document (201109_12.pdf)
Received November 11, 2009; revised February 23 & May 24 & August 16, 2010; accepted September 23, 2010.
Communicated by Chung-Ta King.
* This paper was an extended version of a paper appeared in the 9th IEEE International Symposium on Object and
Component-Oriented Real-Time Distributed Computing, April 24-26, 2006, Kolon Hotel, Gyeongju, Korea, and
was partially supported by the National Science Council of Taiwan, R.O.C., under Grant No. NSC 100-2628-
E-011-014-MY3-.