Keywords: DFT, low power, scan chain, compression, test data volume
Received March 3, 2010; revised July 21, 2010; accepted September 7, 2010.
Communicated by Yao-Wen Chang.
| Previous | [ 1] | [ 2] | [ 3] | [ 4] | [ 5] | [ 6] | [ 7] | [ 8] | [ 9] | [ 10] | [ 11] | [ 12] | [ 13] | [ 14] | [ 15] |
¡@
CHIA-YI LIN AND HUNG-MING CHEN
Department of Electronics Engineering
National Chiao Tung University
Hsinchu, 300 Taiwan
This paper proposes a generic multi-dimensional scan shift control concept for multiple
scan chain design. Multiple scan chain test scheme provides very low scan power by
skipping (selectively load/unload) many long scan chain switching activities. Based on
the two-dimensional scan shift control, we can achieve low test power with simple and
small overhead structure. We can further extend the scheme to a generic N dimension test
scheme. The proposed scheme skips many unnecessary don't care (X) patterns to reduce
the test data volume and test time. The experimental results of the proposed 2-D scheme
achieve significant improvement in shift power reduction, test volume and test time reduction.
Compared with traditional single scan chain design, the large benchmark b17 of
ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time
with little area overhead, around 1% routing overhead, and the power reduction is over
97%.
Received March 3, 2010; revised July 21, 2010; accepted September 7, 2010.
Communicated by Yao-Wen Chang.