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In this paper, complementary Huffman coding techniques are proposed for test data compression/decompression of complex SOC designs during manufacturing testing. Instead of the compatible relationship between test data blocks, complementary features between test blocks are also exploited. Based on this property, more test data blocks can share the same codeword and the size of the modified Huffman tree can be reduced. This will not only reduce the area overhead of the decoding circuitry but also substantially increase the compression ratio. A graph model is also proposed for don¡¦t-care assignment of test cube. This problem can be transformed to the clique partitioning problem whose complexity is basically NP-hard. Therefore, in order to exploit the compatible and complementary relationships between test blocks, a heuristic algorithm is proposed for filling test cubes. Thereafter, given the set of test vectors, two algorithms are proposed for complementary Huffman encoding. The compression ratio and hardware overhead of the decoding circuitry are analyzed. According to experimental results, the area overhead of the decompression circuit is lower than that of the full Huffman coding technique. However, it is a little bit higher than that of the selective Huffman coding technique. Moreover, the compression ratio is higher than that of the selective and optimal selective Huffman coding techniques.

Keywords: test compression, test patterns, system chip, compatibility, complementary compatibility, NP-hard

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Received April 7, 2010; revised June 23, 2010; accepted August 26, 2010.
Communicated by Yao-Wen Chang.