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Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP. This paper uses comprehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC performance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we improve the IPC performance of a voice over IP (VoIP) phone. Experimental results demonstrate that the GPP workload decreases significantly by 35% without sacrificing the functionalities and voice quality of the VoIP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.

Keywords: multi-core, inter-processor communication, performance evaluation, embedded system, heterogeneous multi-core processor

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Received June 17, 2010; revised December 21, 2010 & March 23 & May 18, 2011; accepted July 13, 2011.
Communicated by Tei-Wei Kuo.
^* This work was supported by MediaTek Inc. and the National Science Council of the Republic of China for financially under Contracts No. 100-2219-E-009-022, 100-2220-E-009-038, NSC 99-2220-E-009-045-, NSC 99-3113-P-006-004, and NSC99-2915-I-009-064.