Previous [ 1] [ 2] [ 3] [ 4] [ 5] [ 6] [ 7] [ 8] [ 9] [ 10]

@

Journal of Information Science and Engineering, Vol. 28 No. 4, pp. 895-909 (September 2012)

Enhancing Visual Rendering on Multicore Accelerators with Explicitly Managed Memories*

KYUNGHEE CHO1, SEONGGUN KIM2 AND HWANSOO HAN2,+
1S-Core Corporation
Seongnam, 463-02 Korea
2School of Information and Communication Engineering
Sungkyunkwan University
Suwon, 440-746 Korea

Recent electronic devices are equipped with processors extended with multicore accelerators to take advantage of the powerful performance from acceleration co-processors. Applications on such high-end electronic products require capability to run graphic-rich applications. Scalable acceleration co-processors are frequently designed as multicores with explicitly managed memories. Such multicore architectures require sophisticated data management among the main memory and the local memories to fully exploit their potential performance. Ray tracing is a high quality rendering algorithm in computer graphics and has potentially many parallelism to exploit. On the explicitly managed memory hierarchies, however, ray tracing with complex data structures tends to suffer from irregular memory accesses and inefficient data management. Compared to other acceleration structures for ray tracing, grid structure is simple to manage but commonly regarded to produce too slow algorithms. However, recent improvements on grid structure with SIMD optimizations show comparable performance with kd-tree structure, which is one of the fastest acceleration structures. We introduce a grid structure based parallel ray tracer on a processor with a multicore accelerator. We adopt SIMD optimizations and double buffering to enhance the performance of grid-based ray tracer and propose a macrocell structure over the grid to fully exploit the memory bandwidth. In our experiment, our ray tracing scheme shows comparable performance with BVH-based ray tracer.

Keywords: ray tracing, multicore accelerator, grid structure, DMA latency hiding, explicitly managed memory

Full Text () Retrieve PDF document (201209_05.pdf)

Received May 31, 2011; accepted March 31, 2012.
Communicated by Jiman Hong, Junyoung Heo and Tei-Wei Kuo.
* This work was supported by the Ministry of Education, Science, and Technology, Korea under NRF Grant No. NRF-2009-0084870 and by the Ministry of Knowledge Economy, Korea under NIPA ITRC program No. NIPA-2012-H0301-12-1011.
+ Corresponding author.