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Journal of Information Science and Engineering, Vol. 30 No. 3, pp. 819-833 (May 2014)


Reduced Power Consumption via Fewer Memory Accesses for Deep Packet Inspection*


HANSOO KIM1,2, YOUNGLOK KIM2 AND JU WOOK JANG2,+
1Digital Technology and Biometry Division
National Forensic Service
Yangcheongu, Seoul 158-707, Korea
2Electronic Engineering Department
Sogang University
Mapogu, Seoul 121-742, Korea

We propose a new mapping scheme for AC-DFA tries to be used in FPGA implementation of deep packet inspection (DPI). Our scheme greatly reduces number of memory accesses which are responsible for most of the power consumption in DPI. We vary strides in the construction of AC-DFA tries in such a way that the number of memory accesses is minimized without increasing the memory space. Compared with the state-of-the-art DPI architecture [3], our scheme shows 34% reduction in power consumption and 14% reduction in memory space.

Keywords: intrusion detection, pattern matching, variable stride, deep packet inspection, Snort

Full Text () Retrieve PDF document (201405_16.pdf)

Received November 19, 2012; revised February 17, 2013; accepted March 4, 2013.
Communicated by Cho-Li Wang.
* This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (NRF-2013R1A1A2011856).
+ Corresponding author: jjang@sogang.ac.kr.